Chip

3ue Chip Interfaces

Wired Interface                                                                              

•         USB 1.1 control unit and transceiver with max. 8 IN / 8 OUT endpoints

•          I2C controller supporting Master 100K / 400K data rate

•          UART 9600 / 19200 / 38400 / 115200  8 bits, no, 1 stop, RTS/CTS, ON/OFF

•          ISO 7816 baud rate in the range 20 to 300 kb/s, external clock

•          H-bridge circuitry can drive 1 bidirectional or 2 directional DC motors

•          ADC 6 channels 10 bit resolution (effective 7 bits)

•          DAC 1 channel 16 bit

•          parallel GPIO 14 input or output programmable

•          battery power control 2 cell Alkaline or NiMH pack

•          audio CODEC G711 µ low and G726 4 Bit

Wireless Interface                                                                          

•         ISM 2,402 ... 2,482 GHz

•         40 channels with 2 MHz band

•         TX power 0 dBm

•         Rx sensitivity –89 dBm

•         range 30 to 100 m

•         modulation GFS

•         bit rate 4/3 MHz

•         Adaptive Frequency-Hopping ( AFH )

•         quality of Service with Forward Error Correction ( FEC )

•         Cyclic Redundancy Check ( CRC )

•         data with Automatic Repeat reQuest ( ARQ )

Possible Chip Construction Forms                                             

 The 3ue chip can be provided in three differing construction forms:

1. The “3ue dev chip“ is designated for the development of firmware and prototypes. It is a RAM master with 64 kbyte code size.

2. The „3ue full chip“ is developed for large-sized applications with analogue and audio interfaces.

3. The „3ue digital chip“ is a cost-effective alternative in cases where only digital interfaces are required for the application.

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